The present invention relates to a circuit and method for built-in self-test (BIST) and built-in self-repair (BISR) for a memory circuit in a semiconductor integrated circuit device.
Recently, core-based integrated circuit (IC) designs are drawing great attention, as the system-on-a-chip (SOC) design style gains momentum as a new design trend. Accordingly, a memory core or an analog core as well as a central processing unit (CPU) core are frequently used in the IC design. With the trend of SOC design, a complex circuit or system chip such as a CPU requires embedded memories of ever-higher capacity to improve system bandwidth.
Modern technology is capable of achieving high memory capacity while requiring a relatively small die size. Since embedded memories in a circuit have relatively higher complexity and share more signals than other logic blocks, they have higher failure rates. In order to solve this problem, designers commonly add redundancy to the embedded memory.
Semiconductor memory devices are commonly tested by an external memory tester or Automatic Test Equipment (ATE) which physically repairs detected faulty memory cells (for example through laser zapping) through a software repair algorithm, after determining whether the faulty memory cells are repairable or not. To test the SOC according to the above-mentioned method, a core and an embedded memory must be tested separately, and for this reason additional external pins are required. As a result, the SOC test becomes more complex and production cost of the SOC is high.
To address this issue, the SOC commonly comprises a built-in self test (BIST) circuit for performing self-test, and a built-in self repair (BISR) circuit for performing self-repair. The BISR circuit includes a repair algorithm for determining whether the faulty memory cells are repairable or not, and for performing logical repair through software. As described above, the repair method of the BISR circuit is different from the external memory tester or the ATE performing physical repair. An embodiment of above described self-test and self-repair becomes an essential part in recent processor design techniques developing into the SOC. Examples of the BIST circuit and BISR circuit can be found in U.S. Pat. No. 5,920,515 to Shaik et al., issued on July 1999, REGISTER-BASED REDUNDANCY CIRCUIT AND METHOD FOR BUILT-IN SELF-REPAIR IN A SEMICONDUCTOR MEMORY DEVICE; and U.S. Pat. No. 5,987,632 to Irrinki et al., issued on November 1999, METHOD OF TESTING MEMORY OPERATIONS EMPLOYING SELF-REPAIR CIRCUITRY AND PERMANENTLY DISABLING MEMORY LOCATIONS.
Generally, repair methods employing the redundancy cells determine which word line and bit line of the faulty memory cells are replaced to the redundancy cells through a depth first search (DFS), case by case, by constructing a binary search tree with word lines (i.e., row addresses) and bit lines (i.e., column addresses) of the faulty memory cells via software. In this case, the technique consumes O(2n) of test time, meaning that the operation takes 2n of time, assuming the time required to execute one operation (for example, multiplication) is n. The required time forms an exponential function against the row and column redundancies and distribution of the faulty memory cells. Thus, the repair method is not efficient when the number of the redundancies is great and when the memory includes many faulty memory cells. This problem is referred to as an xe2x80x9cNP-completenessxe2x80x9d problem. To solve the problem, a heuristic method is used. The heuristic method solves a given problem through an experiential knowledge obtained by trial and error. If any algorithm is adopted in the NP-completeness problem, it may efficient to restrict a range of the problem to within extremely narrow limits. In that case, it is impossible to embody the NP-completeness problem to hardware without restricting the limits.
For this reason, some SOCs embedding the BISR circuit restrict the limits to be repaired. For example, the numbers of the row and column redundancies are restricted to within 1, respectively. In case that the respective redundancies are one or one pair, the structure of the BISR circuit becomes simple. In that case, the SOC has a restriction that the SOC can repair only one row and one column.
However, considering the tendency that SOC requires an embedded memory with much higher capacity, additional redundancies are required to repair any additional faulty memory cells occurring in the embedded memory. If the faulty memory cells of the embedded memory are not repaired completely, the reliability of the SOC can be adversely affected by faulty memory cells of the relatively inexpensive embedded memory, even though the relatively expensive core such as a central processing unit (CPU) is fault free.
A novel BISR circuit and a repair method are therefore required to repair the faulty memory cells of an embedded memory having multiple redundancies, in a more precise manner.
It is therefore an object of the present invention to provide an integrated circuit semiconductor device having a BISR circuit for an embedded memory with multiple redundancies.
It is another object of the invention to provide a repair method of a BISR circuit for an embedded memory with multiple redundancies.
In order to attain the above objects, according to an aspect of the present invention, there is provided an integrated circuit semiconductor device comprising an embedded memory including multiple row and column redundancies; a built-in self-test circuit for detecting faulty memory cells of the memory; and a built-in self-repair circuit for storing the detected faulty memory cell information by splitting information into row information and column information, determining repair methods of the faulty memory cells in response to the row and column information, and generating repaired addresses to the memory in response to the determined repair methods.
The built-in self-repair circuit preferably includes a built-in self-repair controller for controlling operation of the built-in self-repair circuit; a first data storing means including a plurality of entries having a plurality of data fields, for storing row addresses of the faulty memory cells and the number of the faulty memory cells occurring at a common row address; a first logic unit for storing the row addresses and the number of the faulty memory cells to the first data storing means under control of the built-in self-repair controller; a second data storing means including a plurality of entries having a plurality of data fields, for storing column addresses of the faulty memory cells and the number of the faulty memory cells occurring at the same column address; a second logic unit for storing the column addresses and the number of the faulty memory cells to the second data storing means under control of the built-in self-repair controller; a third logic unit for storing entry locations of opposite data storing means storing column and row addresses corresponding to row and column addresses of the first and second data storing means, and for decreasing the number of faulty memory cells stored at the entry locations of the opposite data storing means under control of the built-in self-repair controller, and an address checker for generating repaired row and column addresses to the memory in response to the row and column addresses of the faulty memory cells under control of the built-in self-repair controller.
The built-in self-repair circuit preferably first determines the repair methods of either of the first data storing means or the second data storing means, depending on which of the first and second data storing means has fewer entries. The built-in self-repair circuit may also determine the repair methods of the first or second data storing means by selecting entries composing the first or second data storing means in order of the number of the stored faulty memory cells.
The third logic unit preferably decreases the number of the faulty memory cells stored in the opposite data storing means appointed by the selected entry by 1 when one or more entries are selected to determine the repair methods, and deletes the entry of the opposite data storing means when the decreased number of the faulty memory cells is zero.
Each entry included in the first data storing means preferably comprises a first data field for indicating validity of the row information stored in the entry; a second data field for storing the row address of the faulty memory cells; a third data field for storing the number of the faulty memory cells having the same row address stored in the second data field; a fourth data field for storing the entry location of the second data storing means storing the column address corresponding to the row address of the faulty memory cells stored in the second data field; and a fifth data field for storing determined repair method of the faulty memory cells. The third data field preferably includes └log2C┘+1 bits, and the fourth data field includes ┌log2(C+CR)┐ bits as much as C, when the memory includes R row redundancies and C column redundancies. The third data field may further comprise of C+1 bits including a least significant bit being set to 1 which is shifted to left whenever the faulty memory cell having the same row address is detected, and the fourth data field is preferably composed of C bits for indicating the entry location as bit flags, when the memory includes R row redundancies and C column redundancies.
Each entry included in the second data storing means comprises a first data field for indicating validity of the column information stored in the entry; a second data field for storing the column address of the faulty memory cells; a third data field for storing the number of the faulty memory cells having the same column address stored in the second data field; a fourth data field for storing the entry location of the first data storing means storing the row address corresponding to the column address of the faulty memory cells stored in the second data field; and a fifth data field for storing determined repair method of the faulty memory cells.
The third data field may be composed of └log2R┘+1 bits, and the fourth data field is composed of ┌log2 (R+RC)┐ bits as much as R, when the memory includes R row redundancies and C column redundancies. Optionally, the third data field may be composed of R+1 bits including a least significant bit being set to 1 which is shifted to left whenever the faulty memory cell having the same column address is detected, and the fourth data field may be composed of R bits for indicating the entry location as bit flags, when the memory includes R row redundancies and C column redundancies.
According to another aspect of this invention, there is provided a repair method of a BISR circuit for an embedded memory with multiple redundancies comprising the steps of: filling row/column information to first/second data storing means, respectively, wherein the row/column information include row/column addresses of faulty memory cells, the number of the faulty memory cells having the same row/column addresses, and entry location of opposite data storing means storing column/row addresses corresponding to the respective row/column addresses; determining repair methods of the faulty memory cells as much as the number of row or column redundancies by selecting entry composing the first or the second data storing means in order of the number of the faulty memory cells stored in the entry, and decreasing the number of the faulty memory cells stored in the entry location of the opposite data storing means appointed by the selected entry; and generating repaired addresses to the memory according to the determined repair methods.
In a preferred embodiment, each entry included in the first data storing means comprises: a first data field for indicating validity of the row information stored in the entry; a second data field for storing the row address of the faulty memory cells; a third data field for storing the number of the faulty memory cells having the same row address stored in the second data field; a fourth data field for storing the entry location of the second data storing means storing the column address corresponding to the row address of the faulty memory cells stored in the second data field; and a fifth data field for storing the determined repair method of the faulty memory cells.
Each entry included in the second data storing means preferably comprises a first data field for indicating validity of the column information stored in the entry; a second data field for storing the column address of the faulty memory cells; a third data field for storing the number of the faulty memory cells having the same column address stored in the second data field; a fourth data field for storing the entry location of the first data storing means storing the row address corresponding to the column address of the faulty memory cells stored in the second data field; and a fifth data field for storing determined repair method of the faulty memory cells.
The step for filling row/column information to the first/second data storing means preferably comprises the steps of: determining whether a row address of a faulty memory cell is stored in the first data storing means; if the row address of the faulty memory cell is stored in the first data storing means, increasing the number of faulty memory cells by 1 stored in the third data field of the first data storing means, and storing an entry location of the second data storing means to the fourth data field; if the row address of the faulty memory cell is not stored in the first data storing means, storing the row address to the first data storing means, and storing the entry location of the second data storing means to the fourth data field; determining whether a column address of the faulty memory cell is stored in the second data storing means; if the column address of the faulty memory cell is stored in the second data storing means, increasing the number of faulty memory cells by 1 stored in the third data field of the second data storing means, and storing an entry location of the first data storing means to the fourth data field; and if the column address of the faulty memory cell is not stored in the second data storing means, storing the column address to the second data storing means, and storing the entry location of the first data storing means to the fourth data field.
The step for determining repair methods preferably comprises the steps of: a) selecting either the first data storing means or the second data storing means having fewer entries; (b) determining a repair method of the selected data storing means by selecting the entry in order of the number of the faulty memory cells; (c) decreasing the number of the faulty memory cells stored in the entry location of the opposite data storing means appointed by the selected entry; (d) repeating the (b) and (c) steps as mant times as the number of the row/column redundancies corresponding to the selected data storing means; (e) selecting either the first data storing means or the second data storing means having much entries; and (f) repeating the (b) and (c) steps as much as the number of the row/column redundancies corresponding to the selected data storing means.
The determined repair methods preferably employ the row redundancies and/or the column redundancies. The entry of the opposite data storing means is preferably deleted when the decreased number of faulty memory cells is zero.